This one is closed
Live roles like this one
Get new “W2 RTL Design” roles by email
One email a day with what is new in "W2 RTL Design". Nothing new, no email.
We confirm the address first, and every mail carries an unsubscribe link. Alerts are ours, not a third party's.
Why this grade
This listing scored 27/100, which is an F. It lost the most ground on pay transparency.
- Description depth 20 / 20 How much the posting actually says about the work, measured in characters of real text.
- Remote clarity 8 / 15 Whether "remote" means anywhere, or is quietly restricted to one country.
- Corroboration 5 / 10 Whether more than one source carries this listing.
- Freshness 4 / 15 How recently it was posted. Older postings are likelier to be filled or abandoned.
- Role specificity 0 / 10 Whether the listing is tagged well enough to tell what the role actually is.
- Pay transparency 0 / 25 A published salary range, worth more than any other single factor because it is what a candidate cannot find out without applying.
-10 Ghost-job penalty — Deducted for signals that this posting may not be a real, currently-open role — staleness, repeated relisting, or talent-pool language.
Every figure above is arithmetic over the posting itself — its salary field, its text, its age, its tags and how many sources carry it. How the grades work →
seeking an RTL Design Engineer for a fully remote 12-month contract engagement focused on custom silicon development. The ideal candidate will own the full micro-architecture and RTL design lifecycle for complex digital blocks, operating independently from day one. This role requires hands-on fluency in SystemVerilog and recent experience with memory controller design and SoC integration.
Responsibilities
- Own micro-architecture definition derived from high-level functional specifications
- Develop and implement RTL for complex digital blocks using SystemVerilog/Verilog
- Drive digital block control logic and IP integration
- Participate in subsystem-level architecture alignment discussions
- Support design sign-off activities including CDC, RDC, lint, and synthesis readiness checks
- Collaborate closely with Design Verification (DV) teams for closure and debug
- Take full project lifecycle ownership with minimal supervision
Key Qualifications
- Strong, current expertise in RTL design using SystemVerilog and/or Verilog
- Demonstrated ability to independently define micro-architecture from functional specs
- Recent hands-on experience designing custom RTL blocks such as controllers, DMAs, or SoC bus bridges
- Solid understanding of memory controllers, including HBM, DDR4, or DDR5
- Experience with SoC integration and digital subsystem design
- Proficiency with IP integration and block-level ownership
- Working knowledge of sign-off flows including CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing)
- Experience designing IPs with multiple clock domains
- Ability to operate independently with no ramp-up time required
Preferred Qualifications
- Experience in subsystem-level RTL development
- Exposure to Die-to-Die (D2D) logic design
- Prior experience working directly with major hyperscaler silicon teams
Originally posted on Himalayas
Apply for this role Opens himalayas.app — the link as listed; we have not yet verified it is the employer's own page
Quick question · anonymous · one tap
Would you apply to this job?
Answer to see what other job seekers said.
Your turn · no account needed
Help the next applicant
You may know something about this listing that we cannot see from here. One tap. No account needed. Signed-in reports earn points once the evidence agrees with you.
I know what it pays
Sign in with Google to earn points for reports — 100 confirmed points buy a week of Early Access.
Where this listing came from
- 05 Aug 2026 Himalayas first sighting
Seen on 1 board over 0 days.