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Why this grade
This listing scored 63/100, which is a C. It lost the most ground on pay transparency.
- Description depth 20 / 20 How much the posting actually says about the work, measured in characters of real text.
- Freshness 12 / 15 How recently it was posted. Older postings are likelier to be filled or abandoned.
- Pay transparency 12 / 25 A published salary range, worth more than any other single factor because it is what a candidate cannot find out without applying.
- Remote clarity 8 / 15 Whether "remote" means anywhere, or is quietly restricted to one country.
- Role specificity 6 / 10 Whether the listing is tagged well enough to tell what the role actually is.
- Corroboration 5 / 10 Whether more than one source carries this listing.
Every figure above is arithmetic over the posting itself — its salary field, its text, its age, its tags and how many sources carry it. How the grades work →
yc-startup vc-backed
The Mission
Zettascale Computing is building the highest-performance, most energy-efficient AI chips for artificial superintelligence to accelerate discovery and further humanity's understanding of the universe.
We are a high-agency, deeply technical, and intensely mission-driven founding team. We value first principles thinking, intellectual honesty, speed, and full ownership.
The Role
Be part of a small team building Zettascale Computing's silicon efforts from FPGA prototype through tapeout and bring-up. You will set technical direction across architecture, RTL, verification, tooling, and timing closure, build the silicon team as the company grows, and partner closely with the PCB, interconnects, racks and pods, and software teams.
What You Will Build
- Lead development and optimization of the FPGA prototype of our XPU
- Design and review the RTL that becomes our first ASIC
- Build the lint, simulation, synthesis, timing, and verification flows
- Make architecture decisions across compute, memory, on-chip interconnect, and control
- Drive the design to tapeout and bring-up
What You Bring
- Strong digital design fundamentals, including RTL, pipelining, clocks, resets, latency, throughput, and clean microarchitecture
- Hands-on FPGA experience taking real designs from RTL to a working board
- Synthesizable SystemVerilog or Verilog you are proud of
- Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC
- Experience automating hardware flows with Python, Tcl, Make, Nix, or similar tools
- Comfort designing compute datapaths and memory systems around bandwidth and latency
- Experience with AI accelerators or low-level AI kernels
- A proven autodidact
Tapeout experience, large FPGA prototypes, high-speed interface integration, formal verification, UVM, cocotb, firmware, drivers, and systems programming are strong advantages.
Expectations
- This is a full-time, in-person role at our San Francisco HQ. It is not remote or hybrid
- You move quickly, take broad ownership, and prefer working hardware over perfect specifications
- We do not track hours. We care about output, quality, and throughput
- Critical tapeout, bring-up, and delivery milestones sometimes require long days and weekends. We expect you to lean in when they do
- You are ready to go all-in and do the work of your life
Compensation and Support
- $200,000 to $300,000 base salary
- 1.00% to 2.00% equity
- Medical, dental, and vision coverage
- 401(k), equipment, and gym support
- Relocation assistance to San Francisco
- Visa sponsorship where feasible
Apply for this role Opens ycombinator.com — the link as listed; we have not yet verified it is the employer's own page
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Where this listing came from
- 02 Oct 2026 Y Combinator first sighting
Seen on 1 board over 1 day.